The invention relates broadly to digital beam controllers for electronically controlled phased array radar systems, and more particularly, to apparatus for minimizing the computational hardware in the beam spreading computational section of the digital beam controller by utilizing generated random digital numbers in the round off operations of the digital computations associated with the elemental spread beam phase commands.
In general, electronically scanned array radar systems include a digital beam controller portion which sequentially computes beam phase command words for the antenna elements of the radar. Usually, the limiting factor of this type of radar is the ability of the antenna phase shifters to linearly follow the computed phase commands accurately. In most radars, the phase command value is computed to a higher degree of accuracy than that which the phase shift can follow. Consequently, most radars like the one described in U.S. Pat. No. 3,500,412, issued to R. G. Trigon on Mar. 10, 1970, for example, employ a round off operation which precedes the linking of the computed phase commands to the antenna element phase shifters. Accordingly, it is generally well known that rounding off of this type causes errors in computation. Individually, these round off errors are normally quite small, but when accumulated with the other computational errors in the radar system, they may, at times, render the composite phase command error to be out-of-specification.
Digital beam controllers are usually comprised of a pencil beam pointing computational section, such as the one described in some detail in the U.S. Pat. No. 3,643,075, issued to W. F. Hayes on Feb. 15, 1972, for example; and a beam spreading computational section, such as the one, described in adequate detail, in the U.S. Pat. No. 3,877,012, issued to E. A. Nelson on April. 8, 1975, for example. The resultant phase commands correspondingly computed from the aforementioned computational sections are coded together to form a composite phase command signal for each of the antenna element phase shifters. The problems associated with round off errors in the pencil beam pointing computational section are pretty well discussed in terms of digital quantization in the U.S. Pat. No. 3,643,075. Hayes, in his disclosure, claims to reduce substantially errors in the pencil beam pointing section as a result of the round off process conducted therein. This method comprises adding random numbers to predetermined residue least significant bits of the computed digital phase command words prior to truncation which apparently averages the round off errors to effectively reduce the mean round off error contribution to the overal beam pointing error. However, neither Hays' nor Nelson's disclosure is directed to round off errors in the beam spreading computational section.
Beam spreading computational sections of the type disclosed in Nelson generally utilize a quadratic non-linear phase function for computing the beam spreading phase commands which are distributed to the elements of a two-dimensioned antenna phase array. Computational round off errors associated with the derivation of the beam spreading phase commands may also contribute to the beam pointing errors. For example, a typical two-dimensioned parabolic type phase function used to compute the phase command for the beam spreading of a phased array radar is shown in the equation below: EQU .phi..sub.N (m,n)=(K.sub.1 m.DELTA.Y+K.sub.2 n.DELTA.Z).sup.2 +(K.sub.3 m.DELTA.Y+K.sub.4 n.DELTA.Z).sup.2 ; (1)
where m.DELTA.Y is the physical location of the phase shifter (m,n) in the horizontal dimension of the radar antenna and n.DELTA.Z is the physical location of the phase shifter (m,n) in the vertical dimension. K.sub.1 (K.sub.2) and K.sub.3 (K.sub.4) are factors related to the vertical (horizontal) parabolic spread factor and to the inertial navigation of the aircraft required to rotationally stabilize the vertical (horizontal) parabolic beam against aircraft motion and the pointing direction of the beam relative to antenna boresight. One known radar system implements the non-linear function denoted in equation (1) above as shown simply in FIG. 1.
Referring to FIG. 1, the values of the factors K.sub.1 .DELTA.Y, K.sub.2 .DELTA.Z, K.sub.3 .DELTA.Y and K.sub.4 .DELTA.Z generally derived by a radar data processor of a well-known variety which is usually functioning in cooperation with an inertial navigation system are respectively provided to digital storage registers 10, 11, 12 and 13 over signal lines 14, 15, 16 and 17. The storage registers 10, 11, 12 and 13 capture the information provided thereto as controlled by the gating signal 19 in a timely fashion derived by a conventional timing and control circuit 21. In this embodiment, the signals 14 through 17 may include digital words of 16 to 19 bits of digitally coded information. The outputs of the digital registers 10 through 14 are respectively coupled to one input of the conventional digital adders 22, 23, 24 and 25. The outputs of the adders 22 through 25 are captured by a corresponding set of digital storage registers 27, 28, 29 and 30 as controlled by the gating signals 32 and 34 also derived by the timing and control circuitry 21. The outputs of the registers 27 through 30 are respectively coupled to the second input of the digital adders 22 through 25. The outputs of the registers 27 and 28 are added together by a digital adder 36 and the outputs of the registers 29 and 30 are added together by another digital adder 38. Up to this point, the computations have been linear in nature. Both output words 40 and 42 of the adders 36 and 38, which may be comprised of 16 to 19 bits, are representative of the linear terms in equation (1) prior to squaring. A round off operation is performed on the digital words 40 and 42 by the round off circuits 44 and 46, respectively, which are described in greater detail hereinbelow. In rounding off, the digital words 40 and 42 may be truncated to 12 bits, for example, over signal lines 48 and 50, respectively. The digital words 48 and 50 are squared by the conventional digital squaring circuits 52 and 53 and their corresponding squared results 55 and 56 are added together by a digital adder 58 to form a spread beam phase command word 60 which may be, in turn, added to a beam pointing phase command word 62 in a digital adder 64 to form the composite phase command word 66. In general, the composite phase command word 66 is also rounded off a round off circuit 68 prior to being distributed to its corresponding associated phase shifter of a radar antenna array (not shown).
Operationally, each new desired beam shaping pattern is supplied to the registers 10 through 13 over signal lines 14 through 17, respectively, and accordingly captured therein as controlled in time by the gating signal 19. Thereafter, the phase commands for the individual antenna elements of the phased array are sequentially computed in accordance with a predetermined sequence. For example, if the phase shifters of the antenna are updated in a per column basis, gate timing pulses on signal line 32 are provided to registers 27 and 29 and the values in registers 10 and 12 are accumulated utilizing adders 22 and 24 and corresponding registers 27 and 29 for as many elements as there are in a column. At the completion of the phase command word computations for each column, a gate timing pulse over signal line 24 is provided to registers 28 and 30 to accumulate the values of registers 11 and 13 in registers 28 and 30, respectively. The pairs of storage registers 27 and 28, and 29 and 30 may be concurrently added together in digital adders 36 and 38, respectively, to form the linear terms 40 and 42 for each sequentially generated phase command word. The subsequent functions operate continuously in response to the sequential formation of linear terms 40 and 42 to form the non-linear two-dimensioned phase command word 60 as exhibited by equation (1). The sequential distribution of each phase command word to its corresponding phase shifter in the antenna array is conducted in a well-known manner. Reference is made to the patents referred to hereinabove for a more detailed description thereof.
Known embodiments for rounding off digital words suitable for use as round off functions of 44 and 46 are exhibited in more specific detail in FIG. 2. The digital words 40 and 42 are provided to one input of conventional digital adders denoted at 80 and 81, respectively. A one-half least significant bit (1/2 LSB) signal is added to each of the digital words 40 and 42 utilizing the adders 80 and 81. The outputs of the adders 80 and 81 are truncated at 82 and 84 to a predetermined number of bits. For example, assume that the digital words 40 and 42 are each 16 bits, then in the adders 80 and 81, a digital one is added to the 13th bit of each word 40 and 42, respectively. The addition results in 16 bit words which may be truncated at 82 and 84 to segregate the 12 most significant bits therefrom at 48 and 50, respectively, whereby the four least significant bits of the adder outputs are discarded. By utilizing this type of round off apparatus, it is determined from the known theories of linear pointing errors that the round off operations applied to the digital words which appear at 40 and 42 are least accurate in the region where all their values are at an integer number of half-quanta and also near where their values are at an integer number of quanta.
In the case of integer multiples of half-quanta, it may be assumed that round off errors denoted by K.sub.5 and K.sub.6 are generated by the round off process of 44 and 46, respectively, and in so assuming equation (2) may be rewritten as: EQU .phi.'.sub.N (m,n)=(K.sub.1 .DELTA.m Y+K.sub.2 n.DELTA.Z+K.sub.5).sup.2 +(K.sub.3 m.DELTA.Y+K.sub.4 n.DELTA.Z+K.sub.6).sup.2 ( 2)
Expanding equation (2), it is found that: EQU .phi.'.sub.N (m,n)=.phi..sub.N (m,n)+{(K.sub.5 K.sub.1 +K.sub.6 K.sub.3)m.DELTA.Y+(K.sub.5 K.sub.2 +K.sub.6 K.sub.4)n.DELTA.Z}+(K.sub.5.sup.2 +K.sub.6.sup.2) (3)
The first term of equation (3) is the desired beam shaping phase command word of equation (1); the second term is a linear term which represents a pointing angle error contribution in the antenna phased array; and the third term is a constant term. If the non-linear phase function .phi.(m,n) is uniformly distributed over the entire face of the antenna, the third term has no contribution to the beam pointing error. However, if the non-linear phase term (m,n) appears only over part of the antenna any, as would be the case in CSC.sup.2 type beam shaping, then the third term would be a non-symmetric error rendering a contribution to the beam pointing error. It is thus shown that round off errors in the beam spreading computational section also contribute to the beam pointing errors and accordingly should be considered in the accuracy of the sizing of the digital words in beam spreading computational sections.
In most high performance electronically controlled phase array radars, it is sometimes essential that the radar beam be updated frequently causing the elemental digital phase command word computations to be performed at relatively high speeds. Consequently, each squaring operation shown in FIG. 2 at 52 and 53 is presently implemented by either a high speed multiplier comprising a known interconnection of medium scale integrated (MSI) logic circuits or a large number of high speed desirably programed integrated memory circuits. In one known radar system which has been sized for the purposes of computational accuracy to use 12 bit digital words at 48 and 50, the digital multipliers at 52 and 53 each comprise approximately 25 MSI circuits to compute a 24 bit word at both 55 and 56. An additional 6 MSI conventional adder circuits are embodied at 58 to add the squared digital words at 55 and 56 to form the beam spreading phase command word at 60 of which only eight bits are generally used. In this same known radar systems, if conventional 512.times.4 programmed read-only-memories of the high speed variety were used to implement the multiplier, it is estimated that it would require approximately 70 MSI circuit chips to provide for the same 8 bit digital word at 60. These types of hardware implementations represent space, cost, and reliability limitations to the specification and operation of the radar system.
One proposed alternative for minimizing the computational hardware of the beam spreading computational section, exemplarily illustrated in FIG. 2, is to reduce the number of bits of the digital words at 48 and 50 by rounding off of the digital words 40 and 42 to a more significant bit level, like 8 bits, for example, However, if this is attempted with the present round off apparatus, described in connection with the embodiment of FIG. 2, the smoothing or averaging effect of the round off operation is not expected to be adequate, in all cases, to reduce the mean error in the beam pointing command words, contributed by the round off operation, to within specification limits. Apparently, errors contributed by the round off operations at 44 and 46 in FIG. 2 have a tendency to peak when the distribution levels of the input digital words 40 and 42 are principally periodically related to integer numbers of half-quanta. As a result, the smearing or smoothing effects of the present round off operation, proposedly do not alleviate the problem of round of error peaking given the one-sided distribution levels of the input digital words. It appears that if the accuracy of the computations could be preserved under all conditions, especially that of round off induced error peaking just described, then the number of bits may be reasonably reduced ultimately leading to a minimization of computational hardware.